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| SPICE Device Model SUD50N025-05P Vishay Siliconix N-Channel 25-V (D-S) MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Model Subcircuit) * Level 3 MOS www..com * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73393 S-50907Rev. A, 16-May-05 www.vishay.com 1 SPICE Device Model SUD50N025-05P Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a www..com Symbol Test Condition Simulated Data 1.8 1013 0.0041 0.0063 0.90 Measured Data Unit VGS(th) ID(on) rDS(on) VSD VDS = VGS, ID = 250 A VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 20 A VGS = 4.5 V, ID = 15 A IS = 30 A, VGS = 0 V V A 0.0042 0.0062 0.90 V Drain-Source On-State Resistancea Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 12 V, VGS = 4.5 V, ID = 50 A VDS = 12 V, VGS = 0 V, f = 1 MHz 3956 820 338 30 10.5 10.5 3600 790 430 30 10.5 10.5 nC pF Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73393 S-50907Rev. A, 16-May-05 SPICE Device Model SUD50N025-05P Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) www..com Document Number: 73393 S-50907Rev. A, 16-May-05 www.vishay.com 3 |
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